1. Related Field
The present invention relates generally to stabilization of clock signals. More particularly the invention relates to a clock regenerator for generating a stabilized output clock signal and a method for the same. The invention also relates to an associated computer program and computer readable medium.
2. Related Art
Traditionally, a so-called phase locked loop (PLL) circuit has been used to make certain that the clock signal of a digital design fulfils specific quality criteria, such as regarding frequency and phase stability. However, the PLL design requires analog components, and therefore cannot be integrated into a purely digital design, for example realized in a field-programmable gate array (FPGA). This is disadvantageous because an all-digital (without analog building blocks) design would, in most cases, be a more cost efficient alternative.
WO93/12600 and U.S. Pat. No. 6,219,396 describe de-jittering designs for regenerating clock signals, and EP 599 311 shows a clock recovery circuit. All three documents represent different forms of PLLs.
Various non-PLL solutions are also known for recovering signals that have deteriorated. Some of these solutions can be employed to stabilize a clock signal having a varying frequency.
Aguiar, R. L. et al., “Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs”, Analog Integrated Circuits and Signal Processing, 43, 159-170, 2005 reveals an all-digital mechanism for selecting a signal having optimal properties. Here, so-called phase picking is used to select the most appropriate sample as the recovered data, or the most appropriate phase as the recovered clock. However, no averaging is performed in respect of the input clock signal.
EP 1 865 649 describes an overall digital clock and recovery solution using both oversampling and tracking. Here, an input data stream is oversampled by a high-frequency clock. The input data stream is tracked by locating transitions between adjacent samples of the oversampled stream and by moving a no-transition area within the oversampled stream wherein no transitions between adjacent samples are found. A resulting recovered data signal is obtained as a central portion of the no-transition area. The recovered clock signal is generated by dividing the high-frequency clock used for said oversampling. However, there is no teaching or suggestion that the average period time of the input clock signal should be determined.
U.S. Pat. No. 4,310,795 discloses a solution for monitoring the characteristics of a periodic signal used in telemetry. Specifically, a circuit is described which measures the average period of a low-frequency periodic signal by counting stepping pulses from a high-frequency pulse generator and resetting pulses from a phase-angle detector monitoring the periodic signal. A first shift register is loaded with a count for each stepping pulse, and an adder at the output of the first shift register emits a signal coding the sum of all stepping pulses. A second shift register is loaded with the output sums of the adder and has a first and last storage cell connected to a subtractor, which emits a signal indicating changes in the average period of the low-frequency signal. Hence, any deviations from a desired frequency can be detected. However, the low-frequency signal as such remains unaltered.
Consequently, various solutions are known for regenerating deteriorated signals. A solution is also known for determining the average period of a cyclic signal. Nevertheless, there is no prior all-digital solution capable of replacing a traditional PLL circuit.